The present invention relates to MOS-gated devices, and more specifically relates to a novel process for the manufacture of P channel MOS-gated devices which has a reduced mask count and a reduced number of critical mask alignment steps.
MOS-gated devices are well known and include such devices as power MOSFETs, IGBTs and MOS-gated thyristors. The manufacturing process for making such devices includes the use of plural masks which are used in photolithography processes to define the patterns of N and P diffusions, polysilicon layers, dielectric layers and contact metals used to form the device. It is very desirable to reduce the number of masks used in the manufacture process and to reduce the number of critical alignments needed between these masks in order to reduce manufacturing costs and possible wafer defects due to the increased handling of wafers and the use of a larger number of mask steps.